1) Field of the Invention
This invention relates generally to fabrication of capacitors in DRAM cells and more particularly to a method for fabricating fence shaped-capacitors with self aligned storage nodes.
2) Description of the Prior Art
Very large scale integration (VLSI) semiconductor technologies have dramatically increased the circuit density on a chip. The miniaturized devices built in and on semiconductor substrate, making up these circuits, are very closely spaced and their packing density has increased significantly. More recent advances in photolithographic techniques, such as phase-shifting masks, and self-aligning process steps have further reduced the device sized and increased circuit density. This has lead to ultra large scale integration (ULSI) with minimum device dimensions less than a micrometer and more than a million transistors on a chip. With this improved integration, some circuit elements experience electrical limitation due to their down sizing.
One such circuit element experiencing electrical limitations is the array of storage cells on a dynamic random access memory (DRAM) chip. These individual DRAM storage cells, usually consisting of a single metal-oxide-semiconductor field-effect-transistor (MOS-FET) and a single capacitor are used extensively in the electronic industry for storing data. A single DRAM cell stores a bit of data on the capacitor as electrical charge. The decrease in cell capacitance caused by reduced memory cell area is a serious obstacle to increasing packing density in dynamic random access memories (DRAMs). Thus, the problem of decreased cell capacitance must be solved to achieve higher packing density in a semiconductor memory device, since decreased cell capacitance degrades read-out capability and increases the soft error rate of memory cell as well as consumes excessive power during low-voltage operation by impeding device operation.
Generally, in a 64 MB DRAM having a 1.5 .mu.m.sup.2 memory cell area employing an ordinary two dimensional stacked capacitor cell, sufficient cell capacitance cannot be obtained even though a higher dielectric constant material, e.g., tantalum oxide (Ta.sub.2 O.sub.5), is used. Therefore, stacked capacitors having a three-dimensional structure have been suggested to improve cell capacitance. Such stacked capacitors include, for example double-stacked, fin-structured, cylindrical, spread-stacked, and box structured capacitors.
Workers in the art are aware of the challenges to produce small high capacitance DRAM capacitors. For example U.S. Pat. No. 5,380,673, Yang et al., shows a method for forming a stacked capacitor which has an additional electrically conducting layer in the polysilicon layer of the bottom electrode. Also, U.S. Pat. No. 5,234,855, Rhodes et al., discloses a method to form stacked comb spacer capacitor (SCSC) having a spiked v-shaped (or comb-shaped) cross-section. The spiked polysilicon structure increases the capacitance by 50%. Others have increased the cell capacitance by forming recesses under the bottom storage electrode thereby increasing the bottom electrode surface area. See U.S. Pat. No. 5,444,010, Park et al.
However, many of the prior art methods require substantially more processing steps or/and planar structures which make the manufacturing process more complex and costly. Also, other process methods rely on etching to a predetermined etch depth which can be quite difficult to control in a manufacturing environment. For example, during plasma etching outgassing, virtual or real leaks, back streaming from pumps and loading effects, to name a few, can change the chemistry of the etching environment in the process chamber, making a calibrated etch time approach difficult to control. Therefore, it is very desirable to develop processes that are as simple as possible and that further increase the cell capacitance.
There is a challenge to develop methods of manufacturing these capacitors that minimize the manufacturing costs and maximize the device yields. In particular, there is a challenge to develop a method which minimizes the number of photoresist masking operations and provides maximum process tolerance to maximize product yields. More particularly, a self-aligned contact node structure is required to increase process tolerances and yields. There is also a challenge to develop a capacitor which is not limited in size by size the photolithographic techniques.